Optimizing Vmin With Path Margin Monitors

Timing uncertainty in modern digital designs can make it difficult to determine the minimum supply voltage.

By Firooz Massoudi and Ash Patel

Choosing the right operating voltage for various digital blocks within a semiconductor device is one of the most important tasks faced by chip designers. Operating voltage has major effects on performance, power consumption, and reliability. Increasing the voltage generally increases performance, but at the cost of more power and higher lifetime operating cost. Many of today’s largest chips are used in portable devices such as smartphones where tradeoffs in performance and battery life are critical to product success. Many chips are also used in safety-critical applications where reliability across the full silicon lifecycle is mandatory. Persistent under-voltage or over-voltage conditions can compromise reliability over time.

The key is selecting the right value for Vmin, which is defined as the minimum supply voltage at which the chip or individual blocks within a chip operate properly. It might seem that this is easy to determine at design time by running static timing analysis (STA) and choosing the minimum voltage that meets the cycle time requirements that, in turn, satisfy the performance targets. However, there is timing uncertainty in modern digital designs, especially at technology nodes below 10nm, that makes it difficult to determine the optimal Vmin. This leads to suboptimal power management and unnecessary guard bands that compromise performance.

The root cause of the problem is that actual silicon timing is affected by factors that are unique to each path in the chip design. A multitude of factors, such as cross talk, phase-locked loop (PLL) jitter, and process, voltage, temperature (PVT) variations across the die, come into play. When a chip is deployed in the field, operating in mission mode, temperate and voltage levels change. Power and timing must be optimized for multiple operating points beyond the PVT corners considered in traditional analysis. The bottom line: there is no guarantee that any identified value for Vmin remains valid throughout the silicon lifecycle.

The only way to address all these challenges is to have monitors inside the chip that can report the magnitude of every parameter that contributes to variability of Vmin. For example, monitoring the margin of the paths inside the chip in mission mode can determine how PVT has changed the margin and help adjust Vmin “on the fly” to optimize power, performance, and reliability. Fortunately, the technology to accomplish this exists today. Many chips use adaptive voltage and frequency scaling (AVFS) to adjust power and performance as needed for current workloads. System controllers that support AVFS can also adjust Vmin based upon field timing measurements, provided by path margin monitor (PMM) intellectual property (IP) within the chip.

PMM units offer fine-grained observability of silicon state non-intrusively while the chip is operating in mission mode. The PMM technology is a key part of Silicon Lifecycle Management (SLM), a holistic approach linking chip design, manufacturing, bring-up, production test, and deployment in the field. Previous blog posts have discussed some of the roles that PMM units play within SLM. For Vmin determination, they measure timing in the actual chip using a mix of functional and synthetic paths.

Functional paths with the tightest timing may not be suitable for PMM insertion since even a small delay might not be tolerable. The designer should select near-critical functional paths as well as paths within key units such as security engines. The paths should have high toggle rates and different timing slack values to create alerts at multiple PVT points. Synthetic (non-functional) paths are valuable to measure the impact of aging or margins. Uncongested regions of the chip can be used for synthetic paths and additional PMM insertions. The mixture of functional and synthetic paths creates a powerful window into the state of the chip for optimal Vmin detection. Around 1000 PMM units are typical in a large, complex chip.

Chip designers employ the following process:

The PMM units generate interrupts whenever the monitored paths cross the timing threshold, which signal the AVFS controller than Vmin must be adjusted.

This process and its benefits for Vmin optimization are fully supported by the Synopsys Silicon Lifecycle Management solution. It includes Synopsys SLM Path Margin Monitor IP to measure timing margins for real paths in-test or in-field. It automates the insertion of PMM IP, placing the PMM units systematically across the die to capture the state of the silicon precisely at a fine physical resolution. Synopsys SLM solution also inserts a PMM controller to manage the configuration and data collection for multiple groups of PMM units. The controller includes internal memory storage, an IEEE 1500/1687 interface for access during chip test, and an APB interface for in-field access.

One of the key benefits of SLM is greater visibility and insight into the operational margins within a chip. Increased process variation and more dangerous aging effects are making this capability mandatory for many applications. The PMM approach has proven to be a valuable way to optimize Vmin values, so much so that it is one of the driving use cases for adopting SLM. Even saving a few mA adds up to huge power savings over the silicon lifecycle, reduction in guard bands boosts performance, and reliability is increased. The automated PMM solution provided by Synopsys pays many dividends for minimal designer investment.

For more information on the complete Synopsys SLM solution, a white paper is available.

Firooz Massoudi is a member of the technical staff at Synopsys.

Ash Patel   (all posts) Ash Patel is director of product marketing at Synopsys.